In modern computing systems, microprocessors or microprocessor cores may access a vast memory address space, which may include a vast number of memory types. For example, an address range of memory in a computer system may store information that can only be accessed by a particular processor or processor core, whereas other address ranges may be accessed by multiple processors or processor cores. Exclusivity of memory is only one attribute that may be associated with a memory address range.
In some prior art systems, memory permissions or access rules may be controlled by the operating system (OS) via virtual memory management in a relatively course granularity of the size(s) of virtual memory pages. The granularity of virtual memory pages varies in size, in some prior art systems, from around 4 kilobytes (KB) through many megabytes (MB) in size. Changing the memory permissions may be an expensive operation in terms of system latency, die real estate, or system cost.
There may be situations in which a program wants to check a memory address before accessing it. For example, a program may check an address before accessing it when debugging programs, checking bounds and type safety in various computer programming languages (e.g., “Java”), profiling programs when analyzing their performance, or other reasons.
If a program checks an address according to a set of rules, it may use at least two prior art approaches: One approach is to use the OS to ensure addresses that do not meet the rules will be detected by the virtual memory management. In this approach the granularity may be restricted to the relatively coarse grain (i.e. large size) of the virtual memory management addressing scheme, and changing the access rules can be very costly. Another prior art approach is to perform a set of checks on an address within the program itself before using the address to access memory. The set of checks can compare the address against any set of rules at any granularity or size. The drawback of this prior art approach is that a substantial performance overhead may be paid for every memory reference to perform the appropriate checks.